Tracing a hierarchical netlist is a popular routine used in conventional Electronic Design Automation (EDA) applications. Conventional netlist tracing applications analyze a circuit by stepping along a path through the netlist from a starting point to an ending point. The analysis evaluates the circuit at each node along the path independently of any prior analyses performed at an earlier node. As a result, the conventional tracing applications often duplicate efforts when the path crosses several instances of a block of circuitry.